The present invention relates to a semiconductor device including a protection device that protects an internal circuit from an abnormal voltage such as that caused by electrostatic discharge.
A semiconductor device generally includes a protection device to protect an internal circuit from an abnormal voltage such as that caused by electrostatic discharge. An example of a protection device is that using a bipolar transistor as disclosed, for example, in Japanese Unexamined Patent Application Publication No. 2009-4763 or Fujii et al., “A novel 80V-class HV-MOS platform technology featuring high-side capable 30V-gate-voltage drift-NMOSFET and a trigger controllable ESD protection BJT,” 2009 IEEE. Another example is that using a thyristor as disclosed, for example, in U.S. Pat. No. 7,566,914 or N. Jensen et al, “Coupled Bipolar Transistors as very robust ESD Protection Devices for Automotive Applications,” EOS/ESD 2003.
More specifically, in the technique disclosed in Japanese Unexamined Patent Application Publication No. 2009-4763, a second base region with a low impurity concentration is formed at a side of a first base region of a bipolar transistor such that the second base region is shallower than the first base region is.
In the technique disclosed in Fujii et al., “A novel 80V-class HV-MOS platform technology featuring high-side capable 30V-gate-voltage drift-NMOSFET and a trigger controllable ESD protection BJT,” 2009 IEEE, a triggering voltage of an npn bipolar transistor functioning as a protection device is controlled by adjusting the distance between a collector and a base of the npn bipolar transistor.
In the technique disclosed in U.S. Pat. No. 7,566,914, two thyristors having different breakdown voltages and different holding voltages are formed on the same substrate and they are wired such that these two thyristors can discharge abnormal voltages in different directions.
In the technique disclosed in N. Jensen et al, “Coupled Bipolar Transistors as very robust ESD Protection Devices for Automotive Applications,” EOS/ESD 2003., a P+ layer is additionally formed at a side of an N+ layer on the upper side of a vertical-type npn bipolar transistor in a thyristor. A lateral-type pnp bipolar transistor is formed by this additional P+ layer and a base (P layer) of the npn bipolar transistor.